An FPGA has a finite routing capacity due to which a fair number of highly dense circuits fail to map on slightly under resourced\narchitecture.The high-interconnect demand in the congested regions is not met by the available resources as a result of which the\ncircuit becomes unroutable for that particular architecture. In this paper, we present a new placement approach which is based on a\nnatural process called diffusion. Our placer attempts to minimize the routing congestion by evenly disseminating the interconnect\ndemand across an FPGA chip. For the 20MCNC benchmark circuits, our algorithm reduced the channel width for 15 circuits. The\nresults showed on average âË?¼33% reduction in standard deviation of interconnect usage at an expense of an average âË?¼13% penalty\non critical path delay. Maximum channel width gain of âË?¼33% was also observed.
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